Fiber optic waveguides enable the serial transmission of information from a driver to a receiver at a relatively long distance (kilometers) and at very high data rates (billions of bits per second). High performance data processing complexes require system buses among its elements to have even higher bandwidths of information transfer (100's of millions of bytes per second). The use of a single conductor, such as a fiber optic waveguide, can be insufficient to serve as such a system bus because of bandwidth limitations.
In the prior art, one solution to the bandwidth problem has been to use multiple conductors in parallel, each conductor carrying a bit of each word to be transmitted. A second solution, known as data striping, entails sending a plurality of data words in parallel over multiple conductors in a serial fashion. Each word is transmitted serially over a single conductor, but it is transmitted in parallel with other words on other conductors.
One challenge in implementing a data striping technique for information transmission is the determination of which of the multiple conductors attached to a computer element form the system bus linking one computer element to another. Some prior art systems al:tempt to use each of the conductors which is physically attached to the computer element. This method has a significant drawback in that if one of the conductors is not operational, the entire bus is rendered inoperable. Other prior art systems have attempted to configure a system bus using only the operational conductors, but these prior art systems have been driven by hardware switches and have been further limited to system buses of two conductors.
When a single conductor has the ability to operate at speeds greater than the device driving the connection, or receiving the signal, a method of pacing the serial connection to the devices at each end of the connection is required. This allows the maximum bandwidth to be derived from the use of each conductor. Prior art acids pacing bits only based on the senders system clock rate difference with respect to the conductor's clock rate. Other prior art requires the messages to be fully buffered at the sender prior to the transmission of the message over the conductor at the conductor's clock rate.